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7-bit programmable, multiphase mobile, cpu synchronous buck controller adp3207a ?2008 scillc. all rights reserved. publication order number: february 2008 C rev. 1 adp3207a/d features 1-, 2-, or 3-phase operation at up to 750 khz per phase 8 mv worst-case differential sensing error over temperature interleaved pwm outputs for driving external high power mosfet drivers enhanced pwm flex mode? for excellent load transient performance automatic power-saving modes maximize efficiency during light load and deeper sleep operation soft transient control reduces inrush current and audio noise active current balancing between output phases independent current limit and load line setting inputs for additional design flexibility built-in, power-good masking supports vid on-the-fly 7-bit digitally programmable 0.3 v to 1.5 v output overload and short-circuit protection with programmable latch-off delay built-in, clock enable output delays cpu clock until cpu supply voltage stabilizes power monitor output signals the total output power of the buck converter applications notebook power supplies for next generation intel? processors general description the adp3207a 1 is a high efficiency, multiphase, synchronous, buck-switching regulator controller optimized for converting notebook battery voltage into the core supply voltage required by high performance intel processors. the part uses an internal 7-bit digital-to-analog converter (dac) to read voltage identification (vid) code directly from the processor that sets the output voltage. the phase relationship of the output signals can be programmed to provide 1-, 2-, or 3-phase operation, allowing for the construction of up to three interleaved buck- switching stages. the adp3207a uses a multimode architecture to drive the logic-level pwm outputs at a programmable switching frequency that can be optimized depending on the output current requirement. the part switches between multiphase and single-phase operation to maximize its effectiveness under all load conditions. in addition, the adp3207a includes a programmable slope function to adjust the output voltage as a function of the load current. as a result, it is always best positioned for a system transient. functional block diagram rt rrpm rampadj v rpm v cc delay oscillator gnd adp3207a en pwrgd ilimit clken vrtt pwm2 fb dprslp stset ss pwm3 sw1 cssum cscomp llset sw2 sw3 csref pwm1 vid6 vid5 vid4 vid3 vid0 vid2 vid1 fbrtn comp crowbar current limit dac + 200mv dac ? 300mv csref 1.7v csref 06582-001 12 13 14 15 23 22 21 19 18 17 33 32 10 9 28 8 27 31 20 1 30 29 2 11 4 7 t tsense 25 24 set reset reset reset en 26 cmp cmp cmp 16 + ? + ? 6 5 34 35 36 37 38 39 40 + ? + ? + ? + ? + ? + ? + ? dprstp psi od dcm soft start power monitor pmon 3 precision reference vid dac soft start/ boot/ deeper sleep control current limit circuit current balancing circuit thermal throttling control uvlo shutdown and bias 1-/2-/3-phase driver logic figure 1. the chip also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power- good output that accommodates on-the-fly output voltage changes requested by the cpu. the adp3207a is specified over the extended commercial temperature range of 0c to 100c and is available in a 40-lead lfcsp. 1 patent no. 6,683,441; other patents pending.
adp3207a rev. 1 | page 2 of 28 | www.onsemi.com table of contents features...............................................................................................1 applications .......................................................................................1 general description..........................................................................1 functional block diagram...............................................................1 revision history................................................................................2 specifications .....................................................................................3 test circuits .......................................................................................6 absolute maximum ratings ............................................................7 esd caution ..................................................................................7 pin configuration and function descriptions .............................8 typical performance characteristics............................................10 theory of operation.......................................................................11 number of phases .......................................................................11 operation modes ........................................................................11 switch frequency setting...........................................................12 output voltage differential sensing ........................................12 output current sensing .............................................................12 active impedance control mode .............................................13 current control mode and thermal balance.........................13 voltage control mode ................................................................13 enhanced pwm mode...............................................................13 power-good monitoring ...........................................................13 power-up sequence and soft start ...........................................14 soft transient...............................................................................14 current-limit, short-circuit, and latch-off protection ......14 changing vid on-the-fly .......................................................15 output crowbar..........................................................................15 reverse voltage protection........................................................15 output enable and uvlo.........................................................16 thermal throttling control......................................................16 power monitor output...............................................................16 application information ................................................................19 setting the clock frequency for pwm mode ............................19 soft-start and current-limit latch-off delay times ...........19 power monitor output...............................................................19 inductor selection.......................................................................19 c out selection..............................................................................21 power mosfets .........................................................................22 ramp resistor selection ............................................................23 setting the switching frequency for rpm mode operation of phase 1..........................................................................................23 current-limit setpoint ..............................................................24 feedback loop compensation design ....................................24 c in selection and input current d i /d t reduction.................25 soft transient setting .................................................................25 selecting thermal monitor components................................25 tuning procedure for adp3207a ............................................25 layout and component placement..........................................27 outline dimensions........................................................................28 ordering guide ...........................................................................28 revision history 02/08 - rev 1: conversion to on semiconductor 2/07revision sp0: initial version
adp3207a rev. 1 | page 3 of 28 | www.onsemi.com specifications vcc = 5 v, fbrtn = gnd, en = vcc, v vid = 0.50 v to 1.5000 v, psi = 1.05 v, dprslp = gnd, dprstp = 1.05 v, llset = csref, t a = 0c to 100c, unless otherwise noted. 1 table 1. parameter symbol conditions min typ max unit voltage error amplifier output voltage range 2 v comp 0.85 4.0 v vid dac dc accuracy v fb ? v vid measured at fb, relative to v vid , see figure 2 ?8 +8 mv v fb (boot) measured at end of start-up 1.192 1.200 1.208 v load line positioning dc accuracy v fb ? v vid measured at fb, relative to v vid , llset ? csref = ?80 mv ?78 ?80 ?82 mv differential nonlinearity 2 ?1 +1 lsb line regulation v fb vcc = 4.75 v to 5.25 v 0.03 % input bias current i fb ?1 +1 a output current i comp fb forced to v out ? 3% 3 ma gain bandwidth product gbw (err) comp = fb 20 mhz slew rate c comp = 10 pf 25 v/s llset input voltage range 2 v llset relative to csref ?200 +200 mv llset input bias current i llset ?70 +70 na fbrtn current i fbrtn 70 400 a vid dac inputs input low voltage v il vid x 0.5 0.3 v input high voltage v ih vid x 0.7 0.5 v input current i in (vid) ?1 a vid transition delay time 2 vid change to fb change 400 ns oscillator frequency range 2 f osc psi = dprstp = 1.05 v, dprslp = gnd 0.3 3 mhz frequency setting f phase t a = 25c, v vid = 1.2000 v, r t = 215 k 170 200 230 khz t a = 25c, pwm3 = vcc, v vid = 1.2000 v, r t = 215 k 300 khz t a = 25c, pwm2 = vcc, v vid = 1.2000 v, r t = 215 k 600 khz rampadj voltage v rampadj i rampadj = 60 a 0.9 1.1 1.2 v rampadj input current range 2 i rampadj in normal mode 1 60 120 a in shutdown, or in uvlo, rampadj = 19 v ?1 +1 a rpm rt voltage v rt r t = 215 k to gnd, v vid = 1.4000 v 1.08 1.2 1.32 v vrpm reference voltage v vrpm i vrpm = 0 a 0.95 1 1.05 v i vrpm = 120 a 1.0 1.06 1.10 v rrpm output current i rrpm v vid = 1.2 v, r t = 215 k ?5.5 a rpm comparator offset v os (rpm) v os (rpm) = v comp ? v rrpm , psi = gnd ?10 mv current-sense amplifier offset voltage v os (csa) cssum ? csref ?0.6 +0.6 mv input bias current (cssum) i bias (cssum) ?30 +30 na input bias current (csref) i bias (csref) ?5 +5 a gain bandwidth product gbw (csa) 10 mhz slew rate c cscomp = 10 pf 10 v/s input common-mode range 2 cssum and csref 0 3.5 v output voltage range 2 0.05 2.0 v output current i cscomp sinking current 350 470 a
adp3207a rev. 1 | page 4 of 28 | www.onsemi.com parameter symbol conditions min typ max unit current balance amplifier common mode range 2 v sw(x)cm ?600 +200 mv input resistance r sw(x) swx = 0 v 25 35 50 k input current i sw(x) swx = 0 v 3 4.5 6 a input current matching i sw(x) swx = 0 v ?5 +5 % zero current switching threshold voltage v dcm (sw1) in dcm mode, dprslp = 3.3 v ?6 mv masked off-time t offmskd measured from pwm turn-off 720 950 ns current-limit comparator ilimit voltage v ilimit r ilimit = 113 k 1.65 1.7 1.75 v ilimit current i ilimit r ilimit = 113 k ?15 a maximum ilimit current 2 ?60 a current-limit threshold voltage v cl v csref ? v cscomp , r ilimit = 113 k, psi = 1.05 v 180 192 210 mv v csref ? v cscomp , r ilimit = 113 k, 1-phase, (pwm2 = vcc), psi = gnd 180 192 210 mv v csref ? v cscomp , r ilimit = 113 k, 2-phase, (pwm3 = vcc), psi = gnd 86 96 107 mv v csref ? v cscomp , r ilimit = 113 k, 3-phase, (neither pwm2 = vcc nor pwm3 = vcc), psi = gnd 55 64 72 mv soft start timer ss current i ss during start-up, v ss < 1.7 v ?10 ?8 ?6 a in normal mode, v ss = 2.0 v ?48 a in current limit, v ss = 2.0 v 1.5 2 2.5 a ss termination threshold voltage v th (ss) during start-up, ss is rising 1.6 1.7 1.8 v ss clamp voltage in normal mode 2.9 v current-limit latch-off voltage v ilo (ss) in current limit, ss is falling 1.6 1.7 1.8 v soft transient control stset current i source (stset) fast exit from deeper sleep, dprslp = 0 v, stset = v dac C 0.3 v ?8 a slow exit from deeper sleep, dprslp = 3.3 v, stset = v dac C 0.3 v ?2.5 a slow entry to deeper sleep, dprslp = 3.3 v, stset = v dac + 0.3 v +2.5 a minimum stset capacitance 2 c stset 100 pf long transient threshold accuracy v os (ssmask) v os (ssmask) = v stset ? v dac 170 mv system interface control inputs psi and dprstp input low voltage v il 0.5 0.3 v input high voltage v ih 0.7 0.5 v dprslp and en input low voltage v il 1.3 1.0 v input high voltage v ih 2.3 1.9 v thermal throttling control ttsense voltage range 2 0 5 v ttsense vrtt threshold voltage vcc = 5 v, ttsense is falling 2.45 2.5 2.55 v ttsense vrtt hysteresis 50 95 mv ttsense bias current ttsense = 2.6 v ?2 +2 a vrtt output low voltage v ol (vrtt) i vrtt (sink) = 400 a 10 500 mv vrtt output high voltage v oh (vrtt) i vrtt (source) = 400 a 4 5 v pmon output frequency f pmon 300 khz
adp3207a rev. 1 | page 5 of 28 | www.onsemi.com parameter symbol conditions min typ max unit magnitude v pmon_mag v csref = 1.1 v 2.17 v filtered output v pmon_filtered v csref_cscomp = 94.5 mv 1.75 1.91 2.07 v v csref_cscomp = 10.5 mv 0.165 0.239 0.310 v power-good comparator undervoltage threshold v csref (uv) relative to nominal dac voltage ?240 ?300 ?360 mv overvoltage threshold v csref (ov) relative to nominal dac voltage 150 200 250 mv output low voltage v pwrgd (l) i pwrgd(sink) = 4 ma 85 250 mv output leakage current i pwrgd v pwrdg = 5 v 3 a power-good delay timer t cpu_pwrgd 7 ms power-good masking time 130 s crowbar threshold voltage v csref (cb) relative to fbrtn 1.65 1.7 1.75 v reverse voltage detection threshold v csref (rv) relative to fbrtn csref is falling ?350 ?300 mv csref is rising ?55 ?3 mv clken output output low voltage i clken (sink) = 4 ma 30 400 mv output leakage current v clken = 5 v, v ss = gnd 3 a od / dcm outputs output low voltage v ol i sink = 400 a 10 500 mv output high voltage v oh i source = 400 a 4 5 v pwm outputs output low voltage v ol (pwm) i pwm(sink) = 400 a 10 500 mv output high voltage v oh (pwm) i pwm(source) = 400 a 4.0 5 v supply supply voltage range v cc 4.5 5.5 v supply current normal mode 4.2 10 ma en = 0 v 70 250 a vccok threshold voltage v ccok vcc is rising 4.4 4.5 v vcc uvlo threshold voltage v ccuvlo vcc is falling 4.0 4.15 v vcc hysteresis 2 260 mv 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). 2 guaranteed by design or bench characterization, not production tested.
adp3207a rev. 1 | page 6 of 28 | www.onsemi.com test circuits 06582-002 1k ? 10nf 113k ? 20k ? ttsense vrtt dcm od pwm1 pwm2 pwm3 sw1 sw2 sw3 en pwrgd pmon clken fb fbrtn comp ss stset dprslp 40 100nf 1 f + 5v 100nf 3.3v 1 adp3207a vid0 vid1 vid2 vid3 vid4 vid5 vid6 dprstp psi vcc ilimit vprm rrpm rt rampadj llset csref cssum cscomp gnd 7-bit code figure 2. closed-loop output voltage accuracy 06582-003 adp3207a gnd cscomp csref 31 19 17 20 5v 39k ? 100nf 1k ? 1.0v cssum 18 vcc v os = cscomp ? 1v 40 figure 3. current-sense amplifier v os 06582-004 31 7 20 adp3207a vcc comp fb llset csref gnd 5v 10k ? 1.0v v vid dac 6 16 17 v dac v dac v fb = fb v = 80mv ? fb v = 0mv figure 4. positioning accuracy
adp3207a rev. 1 | page 7 of 28 | www.onsemi.com absolute maximum ratings table 2. parameter rating vcc C0.3 v to +6 v fbrtn C0.3 v to +0.3 v sw1 to sw3 ?10 v to +25 v rampadj (in shutdown) C0.3 v to +25 v all other inputs and outputs C0.3 v to vcc + 0.3 v storage temperature range ?65c to +150c operating ambient temperature range 0c to 100c operating junction temperature 125c thermal impedance ( ja ) 98c/w lead temperature soldering (10 sec) 300c infrared (15 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise specified, all other voltages are referenced to gnd. esd caution
adp3207a rev. 1 | page 8 of 28 | www.onsemi.com pin configuration and function descriptions 10 9 8 7 6 5 4 3 2 1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 20 19 18 17 16 15 14 13 12 11 en pwrgd pmon fbrtn fb comp ss stset dprslp clken ttsense vrtt dcm pwm2 pwm3 sw1 sw2 sw3 pwm1 od 06582-005 vid0 vid1 vid2 vid5 vid6 dprstp psi vcc vid4 vid3 ilimit vrpm rrpm rt rampadj llset csref cssum cscomp gnd pin 1 indicator adp3207a top view (not to scale) figure 5. pin configuration table 3. pin function descriptions pin no. mnemonic description 1 en power supply enable input. pulling this pin to gnd disables the pwm outputs and pulls the pwrgd output low. 2 pwrgd power-good output. open-drain output that signals wh en the output voltage is outside of the proper operating range. the pull-high voltage on this pin cannot be higher than vcc. 3 pmon power monitor output. after rc filter, the signal is pr oportional to the total output power of the buck converter. 4 clken clock enable output. the pull-high voltage on this pin cannot be higher than vcc. 5 fbrtn feedback return. vid dac and error amplifier reference for remote sensing of the output voltage. 6 fb feedback input. error amplifier input for remote sensing of the output voltage. 7 comp error amplifier output and compensation point. 8 ss soft-start delay setting input. an external capacitor connected between this pin and gnd sets the soft-start ramp-up time and the current-limit, latch-off delay time. 9 stset soft transient slew rate timing input. a capacitor from this pin to gnd sets the slew rate of the output voltage when transitioning between the boot voltage and the programmed vid voltage, and when transitioning between active mode and deeper sleep mode. 10 dprslp deeper sleep control input. 11 ilimit current-limit setpoint. an external resistor from this pin to gnd sets the current-limit threshold of the converter. 12 vrpm rpm mode reference voltage output. 13 rrpm rpm mode timing control input. a resistor between this pin and vrpm sets the rpm mode turn-on threshold voltage. 14 rt multiphase frequency setting input. an external resi stor connected between this pin and gnd sets the oscillator frequency of the device when operating in multiphase pwm mode. 15 rampadj pwm ramp current input. an external resistor from the converter input voltage to this pin sets the internal pwm ramp. 16 llset output load line programming input. the center point of a resistor divider between csref and cscomp is connected to this pin to set the load line slope. 17 csref current-sense reference voltage input. the voltage on this pin is used as the reference for the current-sense amplifier and the power-good and crowbar functions. this pin should be connected to the common point of the output inductors. 18 cssum current-sense summing node. external resistors from each switch node to this pin sum the inductor currents together to measure the total output current. 19 cscomp current-sense compensation point. a resistor and ca pacitor from this pin to cssu m determine the gain of the current-sense amplifier and the positioning loop response time.
adp3207a rev. 1 | page 9 of 28 | www.onsemi.com pin no. mnemonic description 20 gnd ground. all internal biasing and the logic output signals of the device are referenced to this ground. 21 to 23 sw3 to sw1 current balance inputs. inputs for measuring th e current level in each phase. the sw pins of unused phases should be left open. 24 to 26 pwm3 to pwm1 logic-level pwm outputs. each output is connected to the input of an external mosfet driver, such as the adp3419 . connecting the pwm2 and/or pwm3 outputs to vcc causes that phase to turn off, allowing the adp3207a to operate as a 1-, 2-, or 3-phase controller. 27 od multiphase output disable logic output. this pin is actively pulled low when the adp3207a enters single-phase mode or during shutdown. connect this pin to the sd inputs of the phase 2 and phase 3 mosfet drivers. 28 dcm discontinuous current mode enable output. this pin is actively pulled low when the single-phase inductor current crosses zero. 29 vrtt voltage regulator thermal throttling logic output. this pin goes high if the temperature at the monitoring point connected to ttsense exceeds the programmed vrtt temperature threshold. 30 ttsense thermal throttling sense input and ovp disable. the center point of a resistor divider (where the lower resistor is an ntc thermistor) between vcc and gnd is connected to this pin to remotely sense the temperature at the desired thermal monitoring point. grounding ttsense disables ovp function. 31 vcc supply voltage for the device. 32 psi power state indicator input. pulling this pin to gnd fo rces the adp3207a to operate in single-phase mode. 33 dprstp deeper stop control input. 34 to 40 vid6 to vid0 voltage identification dac inputs. when in normal operation mode, the dac output programs the fb regulation voltage from 0.3 v to 1.5 v (see table 6).
adp3207a rev.1 | page 10 of 28 | www.onsemi.com typical performance characteristics 100 200 vid = 1.2875v vid = 1.1500v vid = 0.8375v 2500 2000 1500 1000 0 500 0 300 400 500 600 06582-006 frequency (khz) r t (k ? ) figure 6. master clock frequency vs. r t 150 200 250 300 350 400 0.2 0.4 0.6 0.8 1.0 1.2 1.4 frequency (khz) vid (v) 0 06582-007 figure 7. master clock vs. vid 1.4 1.6 1.8 2.0 2.2 2.4 21 41 61 81 101 121 v (pmon) (v) v (csref - cscomp) (mv) 1 0.2 0.4 0.6 0.8 1.0 1.2 0 v csref = 1.1v v csref = 0.6v 06582-017 figure 8. pmon output vs. v csref_cscomp 06582-008 voltage (mv) 0 50 100 150 200 250 100 200 300 400 500 600 700 800 900 1000 r limit (k ? ) 3-phase psi = high 2-phase psi = low 3-phase psi = low figure 9. current-limit threshold voltage vs. r limit
adp3207a rev. 1 | page 11 of 28 | www.onsemi.com theory of operation the adp3207a combines a multimode pwm/rpm (ramp pulse modulated) control with multiphase logic outputs for use in 1-, 2-, and 3-phase synchronous buck cpu core supply power converters. the internal 7-bit vid dac conforms to intel imvp-6 specifications. multiphase operation is important for producing the high currents and low voltages demanded by todays microprocessors. handling high currents in a single- phase converter puts high thermal stress on the system components, such as the inductors and mosfets. the multimode control of the adp3207a ensures a stable high performance topology for: ? balancing currents and thermals between phases ? high speed response at the lowest possible switching frequency and minimal output decoupling ? minimizing thermal switching losses due to lower frequency operation ? tight load line regulation and accuracy ? high current output by supporting up to 3-phase operation ? reduced output ripple due to multiphase ripple cancellation ? high power conversion efficiency both at heavy load and light load ? pc board layout noise immunity ? ease of use and design due to independent component selection ? flexibility in operation by allowing optimization of design for low cost or high performance number of phases the number of operational phases and their phase relationship is determined by internal circuitry that monitors the pwm outputs. normally, the adp3207a operates as a 3-phase controller. for 2-phase operation, the pwm3 pin is connected to vcc 5 v programs, and for 1-phase operation, the pwm3 and pwm2 pins are connected to vcc 5 v programs. when the adp3207a is initially enabled, the controller sinks 50 a on the pwm2 and pwm3 pins. an internal comparator checks the voltage of each pin against a high threshold of 3 v. if the pin voltage is high due to pull up to the vcc 5 v rail, then the phase is disabled. the phase detection is made during the first three clock cycles of the internal oscillator. after phase detection, the 50 a current sink is removed. the pins that are not connected to the vcc 5 v rail function as normal pwm outputs. the pins that are connected to vcc enter into high impedance state. the pwm outputs are 5 v logic-level signals intended for driving external gate drivers, such as the adp3419 . because each phase is monitored independently, operation approaching 100% duty cycle is possible. in addition, more than one output can operate at a time to allow overlapping phases. operation modes for the adp3207a, the number of phases can be selected by the user as described in the number of phases section, or they can dynamically change based on system signals to optimize the power conversion efficiency at heavy and light cpu loads. during a vid transient or at a heavy load condition, indicated by dprslp going low and psi going high, the adp3207a runs in full-phase mode. all user-selected phases operate in inter- leaved pwm mode, which results in minimal v core ripple and best transient performance. whil e in light load mode, indicated by either psi going low or dprslp going high, only phase 1 of the adp3207a is in operation to maximize power conversion efficiency. in addition to the change of phase number, the adp3207a dynamically changes operation modes. in multiphase operation, the adp3207a runs in pwm mode, with switching frequency controlled by the master clock. in single-phase mode based on the psi signal, the adp3207a swit ches to rpm mode, where the switching frequency is no longer controlled by the master clock, but by the ripple voltage appearing on the comp pin. the pwm1 pin is set to high each time the comp pin voltage rises to a limit determined by the vid voltage and programmed by the external resistor connected between pin vrpm and pin rrpm. in single-phase mode based on the dprslp signal, the adp3207a runs in rpm mode, with the synchronous rectifier (low-side) mosfets of phase 1 being controlled by the dcm pin to prevent any reverse inductor current. thus, the switch frequency varies with the load current, resulting in maximum power conversion efficiency in deeper sleep mode of cpu operation. in addition, during any vid transient, system transient (entry/exit of deeper sleep), or current limit, the adp3207a goes into full phase mode, regardless of dprslp and psi signals, eliminating current stress to phase 1. table 4 summarizes how the adp3207a dynamically changes phase number and operation modes based on system signals and operating conditions.
adp3207a rev.1 | page 12 of 28 | www.onsemi.com table 4. phase number and operation modes psi dprslp vid transient period 1 hit current limit no. of phases selected by user no. of phases in operation operation mode dnc 2 dnc 2 yes dnc 2 n 3, 2, or 1 n pwm, ccm 3 only 1 0 no dnc 2 n 3, 2, or 1 n pwm, ccm 3 only 0 0 no no dnc 2 phase 1 only rpm, ccm 3 only 0 0 no yes dnc 2 n pwm, ccm 3 only dnc 2 1 no no dnc 2 phase 1 only rpm, automatic ccm 3 /dcm 4 dnc 2 1 no yes dnc 2 n pwm, ccm 3 only 1 vid transient period is the time following any vid change, including entrance and exit of deeper sleep mode. the duration of v id transient period is the same as that of pwrgd masking time. 2 dnc means do not care. 3 ccm means continuous conduction mode 4 dcm means discontinuous conduction mode. switch frequency setting master clock frequency for pwm mode the clock frequency of the adp3207a is set by an external resistor connected from the rt pin to ground. the frequency varies with the vid voltage; the lower the vid voltage, the lower the clock frequency. the variation of clock frequency with vid voltage makes v core ripple remain constant and improves power conversion efficiency at a lower vid voltage. figure 6 shows the relationship between clock frequency and vid voltage, parameterized by rt resistance. to determine the switching frequency per phase, the clock is divided by the number of phases in use. if pwm3 is pulled up to vcc, then the master clock is divided by 2 for the frequency of the remaining phases. if pwm2 and pwm3 are pulled up to vcc, then the switching frequency of a phase 1 equals the master clock frequency. if all phases are in use, divide by 3. switching frequency for rpm modeCphase 1 when adp3207a operates in single-phase rpm mode, its switching frequency is not controlled by the master clock, but by the ripple voltage on the comp pin. the pwm1 pin is set high each time the comp pin voltage rises to a voltage limit determined by the vid voltage and the external resistance connected between pin vrpm and pin rrpm. whenever pwm1 pin is high, an internal ramp signal rises at a slew rate programmed by the current flowing into the rampadj pin. once this internal ramp signal hits the comp pin voltage, the pwm1 pin is reset to low. in continuous current mode, the switching frequency of rpm operation is maintained almost constantly. while in discontinuous current mode, the switching frequency reduces with the load current. output voltage differential sensing the adp3207a combines differential sensing with a high accuracy, vid dac, precision ref output and a low offset error amplifier to meet the rigorous accuracy requirement of the intel imvp-6 specification. in steady-state, the vid dac and error amplifier meet the worst-case error specification of 10 mv over the full operating output voltage and temperature range. the cpu core output voltage is sensed between the fb pin and the fbrtn pin. connect fb through a resistor to the positive regulation point, usually the vcc remote sense pin of the microprocessor. connect fbrtn directly to the negative remote sense point, the vss sense point of the cpu. the internal vid dac and precision voltage reference are referenced to fbrtn and have a maximum current of 200 a to guarantee accurate remote sensing. output current sensing the adp3207a provides a dedicated current-sense amplifier (csa) to monitor the total output current of the converter for proper voltage positioning vs. load current and for current-limit detection. sensing the load current being delivered to the load is inherently more accurate than detecting peak current or sampling the current across a sense element, such as the low- side mosfet. the current-sense amplifier can be configured several ways depending on system requirements, including: ? output inductor esr sensing without use of a thermistor for lowest cost ? output inductor esr sensing with use of a thermistor that tracks inductor temperature to improve accuracy ? discrete resistor sensing for highest accuracy the positive input of the csa is connected to the csref pin, which is connected to the output voltage. at the negative input cssum pin of the csa, signals from the sensing element (that is, in case of inductor rdc sensing, signals from the switch node side of the output inductors) ar e summed together by using series summing resistors. the feedback resistor between cscomp and cssum sets the gain of the current-sense amplifier, and a filter capacitor is placed in parallel with this resistor. the current information is then given as the voltage difference between csref and cscomp. this signal is used internally as a differential input for the current-limit comparator.
adp3207a rev. 1 | page 13 of 28 | www.onsemi.com an additional resistor divider connected between csref and cscomp with the midpoint connected to llset can be used to set the load line required by the microprocessor specification. the current information for load line setting is then given as the voltage difference of csref ? llset. the configuration in the previous paragraph makes it possible for the load line slope to be set independent of the current-limit threshold. in the event that the current-limit threshold and load line do not have to be independent, the resistor divider between csref and cscomp can be omitted and the cscomp pin can be connected directly to llset. to disable voltage positioning entirely (that is, to set no load line), tie llset to csref. to provide the best accuracy for current sensing, the csa is designed to have a low offset input voltage. in addition, the sensing gain is set by an external resistor ratio. active impedance control mode to control the dynamic output voltage droop as a function of the output current, the signal proportional to the total output current is converted to a voltage that appears between csref and llset. this voltage can be scaled to equal the droop voltage, which is calculated by multiplying the droop impedance of the regulator with the output current. the droop voltage is then used as the control voltage of the pwm regulator. the droop voltage is subtracted from the dac reference output voltage and determines the voltage positioning setpoint. the setup results in an enhanced feed-forward response. current control mode and thermal balance the adp3207a has individual inputs for monitoring the current in each phase. the phase current information is combined with an internal ramp to create a current balancing feedback system that is optimized for initial current accuracy and dynamic thermal balance. the current balance information is independent of the total inductor current information used for voltage positioning described in the active impedance control mode section. the magnitude of the internal ramp can be set so the transient response of the system become s optimal. the adp3207a also monitors the supply voltage to achieve feed-forward control whenever the supply voltage changes. a resistor connected from the power input voltage rail to the rampadj pin determines the slope of the internal pwm ramp. detailed information about programming the ramp is given in the ramp resistor selection section. external resistors can be placed in series with the sw2 pin and the sw3 pin to create an intentional current imbalance, if desired. such a condition can exist when one phase has better cooling and supports higher currents than the other phase. resistor rsw2 and resistor rsw3 (see the typical application circuit in figure 11) can be used to adjust thermal balance. it is recommended to add these resistors during the initial design to make sure placeholders are provided in the layout. to increase the current in any given phase, users should make rsw for that phase larger (that is, make rsw = 0 for the hottest phase and do not change it during balance optimization). increasing rsw to 500 makes a substantial increase in phase current. increase each rsw value by small amounts to achieve thermal balance starting with the coolest phase. when current limit is reached, the adp3207a switches to full- phase pwm mode, regardless of system signal drpslp and psi , to avoid inrush current stress to the phase 1 power stage. voltage control mode a high gain bandwidth error amplifier is used for the voltage- mode control loop. the noninverting input voltage is set via the 7-bit vid dac. the vid codes are listed in table 6. the non- inverting input voltage is offset by the droop voltage as a function of current, commonly known as active voltage positioning. the output of the error amplifier is the comp pin, which sets the termination voltage for the internal pwm ramps. the negative input, fb, is tied to the output sense location through a resistor, rb, for sensing and controlling the output voltage at the remote sense point. the main loop compensation is incorporated in the feedback network connected between fb and comp. enhanced pwm mode enhanced pwm mode is intended to improve the transient response to a load step up. in traditional pwm controllers, when a load step up occurred, the controller had to wait until the next turn on of the pwm signal to respond to the load change. enhanced pwm mode allows the controller to respond immediately when a load step up occurs. this allows the phases to respond when the load increase transition takes place. ewpm is disabled in rpm operation. power-good monitoring the power-good comparator monitors the output voltage via the csref pin. the pwrgd pin is an open-drain output that can be pulled up through an external resistor to a voltage rail that is not necessarily the same vcc voltage rail of the controller. logic high level indicates that the output voltage is within the voltage limits defined by a window around the vid voltage setting. pwrgd goes low when the output voltage is outside of that window. following the imvp-6 specification, the pwrgd window is defined as ?300 mv below and +200 mv above the actual vid dac output voltage. for any dac voltage below 300 mv, only the upper limit of the pwrgd window is monitored. to prevent false alarm, the power-good circuit is masked during various system transitions, including any vid change and entrance/exit out of deeper sleep. the duration of the pwrgd mask is set by an internal timer to be about 100 s. in conditions
adp3207a rev.1 | page 14 of 28 | www.onsemi.com where a larger than 200 mv voltag e drop occurs during deeper sleep entry or slow deeper sleep exit, the duration of pwrgd masking is extended by an internal logic circuit. power-up sequence and soft start the power-on, ramp-up time of the output voltage is set with a capacitor tied from the ss pin to gnd. the capacitance on the ss pin also determines the current-limit, latch-off time, as explained in the soft transient section. the whole power-up sequence, including soft start, is illustrated in figure 10. in vcc uvlo or in shutdown, the ss pin is held at zero potential. when vcc ramps above the upper uvlo threshold and en is asserted high, the adp3207a enables internal bias and starts a reset cycle that lasts about 50 s to 60 s. next, when initial reset is over, the chip detects the number of phases set by the user and gives a go signal to ramp up the ss voltage. during soft start, the external ss capacitor is charged by an internal 8 a current source. the v core voltage follows the ramping ss voltage up to the v boot voltage level, which is determined by a burnt-in vid co de (the 1.2 v code by imvp-6 specification). while v core is being regulated at v boot voltage, the ss capacitor continues to rise. when the ss pin voltage reaches 1.7 v, the adp3207a asserts the clken signal low, given that the v core voltage is within the power-good window of v boot . the adp3207a reads the vid codes provided by the cpu on vid0 to vid6 input pins. the v core voltage changes from v boot to the vid voltage by a well-controlled soft transition, as introduced in the soft transient section. meanwhile, the ss pin voltage is quickly charged up to a clamp voltage of 2.9 v. the pwrgd signal is not asserted until there is a t cpu_pwrgd delay of about 7 ms, which is fi xed internally by the adp3207a. if either en is taken low or vcc drops below the lower vcc uvlo threshold, then the ss capacitor is reset to ground to be ready for another soft-start cycle. vcc en ss clken pwrgd 1.2v 1.7v 2.9v 06582-009 t cpu_pwrgd v boot v core v vid figure 10. power-up sequence soft transient the adp3207a provides a soft transient function to reduce inrush current during various transitions, including the entrance/exit of deeper sleep and the transition from v boot to vid voltage. reducing the inrush current helps decrease the acoustic noise generated by the mlcc input capacitors and inductors. the soft transient feature is implemented with an stset buffer amplifier that outputs constant sink or source current on the stset pin where an external capacitor is connected. the capacitor is used to program the slew rate of v core voltage during any vid voltage transient. during steady-state operation, both the reference input of the voltage error amplifier and the stset amplifier are connected to the vid dac output. consequently, the stset voltage is a buffered version of vid dac output. when system signals trigger a soft transition, the reference input of the voltage error amplifier switches from the dac output to the stset output, while the input of the stset amplifier remains connected to the dac. the stset buffer input sees the almost instantaneous vid voltage change and tries to track it. tracking is not instantaneous because the buffer slew rate is limited by the source/sink current capability of the stset output. therefore, v core voltage follows the vid dac output voltage change with a controlled slew rate. when the transient period is complete, the reference input of the voltage amplifier switches back to the vid dac output to ensure higher accuracy. table 5 lists the source/sink current on the stset pin for various transitions. by charging/discharging the external capacitor on the stset pin, users actually program the voltage slew rate on the stset pin, and consequently, on the v core output. for example, a 750 pf stset capacitor leads to a 10 mv/s v core slew rate appropriate for a fast exit from deeper sleep, and to a 3.3 mv/s v core slew rate for a slow entry to, or exit from, deeper sleep. table 5. source/sink current of stset system signals vid transient dprslp dprstp stset current entrance to deeper sleep high dnc 1 ?2.5 a fast exit from deeper sleep low dnc 1 +7.5 a slow exit from deeper sleep high high +2.5 a transient from v boot to vid dnc 1 dnc 1 2.5 a 1 do not care. current-limit, short-circuit, and latch- off protection the adp3207a compares the differential output of a current- sense amplifier to a programmable current-limit setpoint to provide current-limiting function. the nominal voltage on the ilimit pin is 1.7 v. the current-limit threshold is set with a resistor connected from the ilimit pin to gnd. in multiphase
adp3207a rev. 1 | page 15 of 28 | www.onsemi.com normal operating mode, the ilimit is internally scaled by using a trimmed 12 k resistor to give a current-limit threshold of 10 mv for each a of ilimit current. for single-phase operation, the current-limit threshold is scaled down even further. the scaling factor is the user-selected number of phases. for example, a 3-phase design scales the current-limit threshold to 3.3 mv/a referred to single-phase operation; a 2-phase design scales the curr ent-limit threshold to 5 mv/a also referred to single-phase operation. during any mode of operation, if the voltage difference between csref and cscomp rises above the current-limit threshold, the internal current- limit amplifier takes control over the internal comp voltage to maintain an average output current equal to the set limit level. during start-up when the output voltage is below 200 mv, a secondary current limit is activated. this is necessary because the voltage swing on cscomp cannot extend below ground. the secondary current-limit circuit clamps the internal comp voltage and sets the internal compensation ramp termination voltage at 1.5 v level. the clamp actually limits voltage drop across the low side mosfets through the current balance circuitry. an inherent per phase current limit protects individual phases in case one or more phases stop functioning because of a faulty component. this limit is based on the maximum normal-mode comp voltage. after a current limit is hit, or following a pwrgd failure, the ss pin is discharged by an internal sink current of 2 a. a comparator monitors the ss pin voltage and shuts off the controller when the voltage drops below about 1.65 v. because voltage ramp (2.9 v ? 1.65 v = 1.25 v) and discharge current (2 a) are internally fixed, current-limit, latch-off delay time can be set by selecting the external ss pin capacitor. the controller keeps cycling the phases during latch-off delay time. if current overload is removed and pwrgd is recovered before the 1.65 v threshold is reached, then the controller resumes normal operation, and the ss pin voltage recovers to 2.9 v clamp level. the latch-off can be reset by removing and reapplying vcc, or by recycling the en pin low and high for a short time. to disable the current-limit, latch-off function, an external pull-up resistor can be tied from the ss pin to the vcc rail. the pull-up current has to override the 2 a sink current of the ss pin to prevent the ss capacitor from discharging down to the 1.65 v latch-off threshold. changing vid on-the-fly the adp3207a is designed to tr ack dynamically changing vid code. as a result, the converter output voltage, that is, the cpu vcc voltage, can change without the need to reset either the controller or the cpu. this concept is commonly referred to as vid on-the-fly (vid otf) transient. a vid otf can occur either under light load or heavy load conditions. the processor signals the controller by changing the vid inputs in lsb incremental steps from the start code to the finish code. the change can be either upwards or downwards steps. when a vid input changes state, the adp3207a detects the change but ignores the new code for a minimum of 400 ns. this keep out is required to prevent reaction to false code that can occur by a skew in the vid code while the 7-bit vid input code is in transition. additionally, the vid change triggers a pwrgd masking timer to prevent a pwrgd failure. each vid change resets and retriggers the internal pwrgd masking timer. as listed in table 5, during an y vid transient, the adp3207a forces a multiphase pwm mode regardless of system input signals. output crowbar to protect the cpu load and output components of the converter, the pwm outputs are driven low, and dcm and od are driven high (that is, commanded to turn on the low-side mosfets of all phases) when the output voltage exceeds an ovp threshold of 1.7 v as specified by imvp-6. turning on the low-side mosfets discharges the output capacitor as soon as reverse current builds up in the inductors. if the output overvoltage is due to a short of the high-side mosfet, then this crowbar action current limits the input supply or causes the input rail fuse to blow, protecting the microprocessor from destruction. once overvoltage protection (ovp) is triggered, the adp3207a is latched off. the latch-off function can be reset by removing and reapplying vcc, or by recycling en low and high for a short time. ovp can be disabled by grounding the ttsense pin. the ovp comparator monitors the output voltage via the csref pin. reverse voltage protection very large reverse currents in inductors can cause negative v core voltage, which is harmful to the cpu and other output components. adp3207a provides reverse voltage protection (rvp) function without additional system cost. the v core voltage is monitored through the csref pin. any time the csref pin voltage is below ?300 mv, the adp3207a triggers its rvp function by disabling all pwm outputs and setting both the dcm and od pins low. thus, all the mosfets are turned off. the reverse inductor current can be quickly reset to 0 by dumping the energy built up in the inductor into the input dc voltage source via the forward-biased body diode of the high- side mosfets. the rvp function is terminated when the csref pin voltage returns above ?100 mv. occasionally, overvoltage crowbar protection results in negative v core voltage, because turn-on of all low-side mosfets leads to very large reverse inductor current. to prevent damage of the cpu by negative voltage, adp3207a keeps its rvp monitoring
adp3207a rev.1 | page 16 of 28 | www.onsemi.com function alive even after ovp latch-off. during ovp latch-off, if the csref pin voltage drops be low ?300mv, then all low-side mosfets are turned off by setting both dcm and od low. the dcm pin and the od pin are set high again when csref voltage recovers above ?100 mv. output enable and uvlo the vcc supply voltage to the controller must be higher than the uvlo upper threshold, and the en pin must be higher than its logic threshold so the adp3207a can begin switching. if the vcc voltage is less than the uvlo threshold, or the en pin is logic low, then the adp3207a is in shutdown. in shutdown, the controller holds the pwm outputs at ground, shorts the ss pin capacitor to ground, and drives dcm and od pins low. proper power supply sequencing during start-up and shutdown of the adp3207a must be adhered to. all input pins must be at ground prior to applying or removing vcc. all output pins should be left in high impedance state while vcc is off. thermal throttling control the adp3207a includes a thermal monitoring circuit to detect if the temperature of the variable resistor (vr) has exceeded a user-defined thermal throttling threshold. the thermal monitoring circuit requires an external resistor divider connected between the vcc pin and gnd. the divider consists of an ntc thermistor and a resistor. to generate a voltage that is proportional to temperature, the midpoint of the divider is connected to the ttsense pin. whenever the temperature trips the set alarm threshold, an internal comparator circuit compares the ttsense voltage to a half vcc threshold and outputs a logic level signal at the vrtt output. the vrtt output is designed to drive an external transistor that, in turn, provides the high current, open-drain vrtt signal that is required by the imvp-6 specification. when the temperature is around the set alarm point, the internal vrtt comparator has a hysteresis of about 100 mv to prevent high frequency oscillation of vrtt. the ttsense pin also serves the function of disabling ovp. in extreme heat, users should make sure that the ttsense pin voltage remains above 1 v if ovp is desired. power monitor output the adp3207a provides power monitoring signal on its pmon pin. the pmon output is a pwm signal at about 300 khz frequency. the magnitude of the pmon pwm signal is twice the voltage of csref pin, and the duty cycle of the pmon pwm is proportional to the total inductor current. therefore, after the rc filter, the averaged pmon signal is proportional to the total output power. see the application information section for the signal size. table 6. vid code table vid6 vid5 vid4 vid3 vid2 vid1 vid0 output (v) 0 0 0 0 0 0 0 1.5000 0 0 0 0 0 0 1 1.4875 0 0 0 0 0 1 0 1.4750 0 0 0 0 0 1 1 1.4625 0 0 0 0 1 0 0 1.4500 0 0 0 0 1 0 1 1.4375 0 0 0 0 1 1 0 1.4250 0 0 0 0 1 1 1 1.4125 0 0 0 1 0 0 0 1.4000 0 0 0 1 0 0 1 1.3875 0 0 0 1 0 1 0 1.3750 0 0 0 1 0 1 1 1.3625 0 0 0 1 1 0 0 1.3500 0 0 0 1 1 0 1 1.3375 0 0 0 1 1 1 0 1.3250 0 0 0 1 1 1 1 1.3125 0 0 1 0 0 0 0 1.3000 0 0 1 0 0 0 1 1.2875 0 0 1 0 0 1 0 1.2750 0 0 1 0 0 1 1 1.2625 0 0 1 0 1 0 0 1.2500 0 0 1 0 1 0 1 1.2375 0 0 1 0 1 1 0 1.2250 vid6 vid5 vid4 vid3 vid2 vid1 vid0 output (v) 0 0 1 0 1 1 1 1.2125 0 0 1 1 0 0 0 1.2000 0 0 1 1 0 0 1 1.1875 0 0 1 1 0 1 0 1.1750 0 0 1 1 0 1 1 1.1625 0 0 1 1 1 0 0 1.1500 0 0 1 1 1 0 1 1.1375 0 0 1 1 1 1 0 1.1250 0 0 1 1 1 1 1 1.1125 0 1 0 0 0 0 0 1.1000 0 1 0 0 0 0 1 1.0875 0 1 0 0 0 1 0 1.0750 0 1 0 0 0 1 1 1.0625 0 1 0 0 1 0 0 1.0500 0 1 0 0 1 0 1 1.0375 0 1 0 0 1 1 0 1.0250 0 1 0 0 1 1 1 1.0125 0 1 0 1 0 0 0 1.0000 0 1 0 1 0 0 1 0.9875 0 1 0 1 0 1 0 0.9750 0 1 0 1 0 1 1 0.9625 0 1 0 1 1 0 0 0.9500 0 1 0 1 1 0 1 0.9375
adp3207a rev. 1 | page 17 of 28 | www.onsemi.com vid6 vid5 vid4 vid3 vid2 vid1 vid0 output (v) 0 1 0 1 1 1 0 0.9250 0 1 0 1 1 1 1 0.9125 0 1 1 0 0 0 0 0.9000 0 1 1 0 0 0 1 0.8875 0 1 1 0 0 1 0 0.8750 0 1 1 0 0 1 1 0.8625 0 1 1 0 1 0 0 0.8500 0 1 1 0 1 0 1 0.8375 0 1 1 0 1 1 0 0.8250 0 1 1 0 1 1 1 0.8125 0 1 1 1 0 0 0 0.8000 0 1 1 1 0 0 1 0.7875 0 1 1 1 0 1 0 0.7750 0 1 1 1 0 1 1 0.7625 0 1 1 1 1 0 0 0.7500 0 1 1 1 1 0 1 0.7375 0 1 1 1 1 1 0 0.7250 0 1 1 1 1 1 1 0.7125 1 0 0 0 0 0 0 0.7000 1 0 0 0 0 0 1 0.6875 1 0 0 0 0 1 0 0.6750 1 0 0 0 0 1 1 0.6625 1 0 0 0 1 0 0 0.6500 1 0 0 0 1 0 1 0.6375 1 0 0 0 1 1 0 0.6250 1 0 0 0 1 1 1 0.6125 1 0 0 1 0 0 0 0.6000 1 0 0 1 0 0 1 0.5875 1 0 0 1 0 1 0 0.5750 1 0 0 1 0 1 1 0.5625 1 0 0 1 1 0 0 0.5500 1 0 0 1 1 0 1 0.5375 1 0 0 1 1 1 0 0.5250 1 0 0 1 1 1 1 0.5125 1 0 1 0 0 0 0 0.5000 1 0 1 0 0 0 1 0.4875 1 0 1 0 0 1 0 0.4750 1 0 1 0 0 1 1 0.4625 1 0 1 0 1 0 0 0.4500 1 0 1 0 1 0 1 0.4375 1 0 1 0 1 1 0 0.4250 vid6 vid5 vid4 vid3 vid2 vid1 vid0 output (v) 1 0 1 0 1 1 1 0.4125 1 0 1 1 0 0 0 0.4000 1 0 1 1 0 0 1 0.3875 1 0 1 1 0 1 0 0.3750 1 0 1 1 0 1 1 0.3625 1 0 1 1 1 0 0 0.3500 1 0 1 1 1 0 1 0.3375 1 0 1 1 1 1 0 0.3250 1 0 1 1 1 1 1 0.3125 1 1 0 0 0 0 0 0.3000 1 1 0 0 0 0 1 0.2875 1 1 0 0 0 1 0 0.2750 1 1 0 0 0 1 1 0.2625 1 1 0 0 1 0 0 0.2500 1 1 0 0 1 0 1 0.2375 1 1 0 0 1 1 0 0.2250 1 1 0 0 1 1 1 0.2125 1 1 0 1 0 0 0 0.2000 1 1 0 1 0 0 1 0.1875 1 1 0 1 0 1 0 0.1750 1 1 0 1 0 1 1 0.1625 1 1 0 1 1 0 0 0.1500 1 1 0 1 1 0 1 0.1375 1 1 0 1 1 1 0 0.1250 1 1 0 1 1 1 1 0.1125 1 1 1 0 0 0 0 0.1000 1 1 1 0 0 0 1 0.0875 1 1 1 0 0 1 0 0.0750 1 1 1 0 0 1 1 0.0625 1 1 1 0 1 0 0 0.0500 1 1 1 0 1 0 1 0.0375 1 1 1 0 1 1 0 0.0250 1 1 1 0 1 1 1 0.0125 1 1 1 1 0 0 0 0.0000 1 1 1 1 0 0 1 0.0000 1 1 1 1 0 1 0 0.0000 1 1 1 1 0 1 1 0.0000 1 1 1 1 1 0 0 0.0000 1 1 1 1 1 0 1 0.0000 1 1 1 1 1 1 0 0.0000 1 1 1 1 1 1 1 0.0000
adp3207a rev.1 | page 18 of 28 | www.onsemi.com vdc v5s v3_3s vdc rtn vr_on imvp6_pwrgd dprs lpvr vrtt# + c1 c20 c25 c8 10 f/25v 8 + r6* r7* 1 1 40 clken + en pwrgd clken fbrtn fb ss stset ttsense vrtt dcm od pwm1 pwm2 pwm3 sw1 sw2 sw3 vid0 vid1 vid2 vid3 vid4 vid5 vid6 vcc ilimit vrpm rrpm rt llset csref cssum gnd + psi r0 + from cpu 06582-010 d3 1n4148 c9 10nf rth1 100k ? , 5% ntc r3 10k ? r4 6.81k ? 1% c11 1 f r r 200k ? 1% u1 adp3207a rampadj cscomp dprslp comp pmon pdprstp cpmon 0.1 f rpmon 10k ? r2 3k ? pmon r1 3k ? c b 330pf c fb 18pf r b 1.67k ? 1% c a 220pf r a 39.2k ? 1% c ss 12nf c stset 390pf r lim 191k ? 1% r rpm 80.6k ? 1% r t 237k ? 1% c12 1nf c cs1 1.8nf c cs2 2nf r cs1 73.2k ? r cs2 165k ? r ph2 84.5k ? 1% r sw1* r sw2* r ph1 84.5k ? 1% c17 4.7 f d3 1n4148 1 2 3 10 9 8 4 7 5 6 in sd crowbar vcc bst sw gnd drvlsd drvh drvl u2 adp3419 u3 adp3419 1 2 3 10 9 8 4 7 5 6 in sd crowbar vcc bst sw gnd drvlsd drvh drvl c14 4.7 f c15 1 f c16 1nf q2 irf7821 q1 irf7821 q3 irf7832 q4 irf7832 l2 360nh/1.1m ? 330 f/ 6m ? 3 panasonic sp series v cc (core) 0.3v to 1.5v 40a v cc (core) rtn 10 f 32 mlcc in and around socket v cc (sense) v ss (sense) rth2 220k ? , 5% ntc l1 360nh/0.85mw q6 irf7821 c19 1nf q8 irf7832 q7 irf7832 q5 irf7821 c18 1 f * for a description of optional components, see the theory of operation section. c13 1nf r5 figure 11. typical 2-phase application circuit
adp3207a rev. 1 | page 19 of 28 | www.onsemi.com application information the design parameters for a typical intel imvp6-compliant cpu core vr application are as follows: ? maximum input voltage (v inmax ) = 19 v ? minimum input voltage (v inmin ) = 7 v ? output voltage by vid setting (v vid ) = 1.150 v ? maximum output current (i o ) = 44 a ? load line slope (r o ) = 2.1 m ? maximum output current step (i o ) = 34.5 a ? maximum output thermal current (i otdc ) = 32 a ? number of phases (n) = 2 ? switching frequency per phase (f sw ) = 280 khz ? duty cycle at maximum input voltage (d min ) = 0.061 ? duty cycle at minimum input voltage (d max ) = 0.164 setting the clock frequency for pwm mode in pwm mode operation, the adp3207a uses a fixed- frequency control architecture. the frequency is set by an external timing resistor (r t ). the clock frequency and the number of phases determine the switching frequency per phase, which directly relates to switching losses and the sizes of the inductors and input and output capacitors. in a 2-phase design, a clock frequency of 560 khz sets the switching frequency to 280 khz per phase. this selection represents a trade-off between the switching losses and the minimum sizes of the output filter components. to achieve a 560 khz oscillator frequency at vid voltage 1.150 v, r t has to be 237 k. alternatively, the value for r t can be calculated using k 5 pf 16 v 1.0 ? + = sw vid t f n v r (1) where 16 pf and 5 k are internal ic component values. for good initial accuracy and frequency stability, it is recommended to use a 1% resistor. soft-start and current-limit latch-off delay times the soft-start and current-limit, latch-off delay functions share the ss pin. consequently, these two parameters must be considered together. the first step is to set c ss for the soft-start ramp. this ramp is generated with a 8 a internal current source. the value for c ss can be set as boot ss ss v t c = a 8 (2) where: v boot is the boot voltage for the cpu, defined in the imvp-6 specification as 1.2 v. t ss is the desired soft-start time, recommended to be below 3 ms in the imvp-6 specification. assuming a desired soft-start time of 2 ms, c ss is 13.3 nf, with the closest standard capacitance at 12 nf. once c ss is chosen, the current-limit latch-off time is equal to 7.2 ms according to a 2 v 2 . 1 ss delay c t = (3) power monitor output the pmon pin output is a 1 mhz pwm signal. as shown in figure 11, the recommended filter is r pmon = 10 k, c pmon = 1 f. after the rc filter, the averaged pmon signal is mv 52.5 o output pmon r w v = (4) where w output is the total output power of the buck converter. inductor selection the choice of inductance determines the ripple current in the inductor. less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the mosfets. however, this allows the use of smaller-size inductors, and for a specified peak-to-peak transient deviation, it allows less total output capacitance. conversely, a higher inductance means lower ripple current and reduced conduction losses but requires larger size inductors and more output capacitance for the same peak-to-peak transient deviation. in a multiphase converter, the practical peak-to-peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. equation 5 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current. equation 6 can be used to determine the minimum inductance based on a given output ripple voltage. ( ) l f d v i sw min vid r ? = 1 (5) (( ) ) ( ) ripple sw min min o vid v f d d n r v l ? ? 1 1 (6) solving equation 6 for a 20 mv peak-to-peak output ripple voltage yields (( ) ) () nh 356 mv 20 khz 280 0.061 1 0.061 2 1 m 2.1 v 1.150 = ? ? l if the ripple voltage ends up being less than the initially selected value, then the inductor can be changed to a smaller value until the ripple value is met. this iteration allows optimal transient response and minimum output decoupling.
adp3207a rev.1 | page 20 of 28 | www.onsemi.com the smallest possible inductor sh ould be used to minimize the number of output capacitors. for this example, choosing a 360 nh inductor is a good starting point and gives a calculated ripple current of 10.7 a. the inductor should not saturate at the peak current of 27.4 a and should be able to handle the sum of the power dissipation caused by the average current of 16 a in the winding and core loss. another important factor in the inductor design is the dcr, which is used to measure phase currents. a large dcr causes excessive power losses, though too small a value leads to increased measurement error. this example uses an inductor with a dcr of 0.89 m. selecting a stan dard inductor once the inductance and dcr are known, the next step is to either design an indu ctor or select a standard inductor that comes as close as possible to meeting the overall design goals. it is also important to have the inductance and dcr tolerance specified to keep the accuracy of the system controlled; 20% inductance and 15% dcr (at room temperature) are reasonable expectations that most manufacturers can meet. power inductor manufacturers the following companies provide surface-mount power inductors optimized for high power applications upon request: ? vishay dale electronics, inc. ? panasonic ? sumida corporation ? nec tokin corporation output droop resistance the inductor design requires that the regulator output voltage measured at the cpu pins drops when the output current increases. the specified voltage drop corresponds to a dc output resistance (r o ). the output current is measured by summing the currents of the resistors monitoring the voltage across each inductor and by passing the signal through a low-pass filter. this summer-filter is implemented by the cs amplifier that is configured with resistors r ph(x) (summer), and r cs and c cs (filter). the output resistance of the regulator is set by the following equations: l x ph cs o r r r r = ) ( (7) cs l cs r r l c = (8) where r l is the dcr of the output inductors. users have the flexibility of choosing either r cs or r ph(x) . due to the current drive ability of the cscomp pin, the r cs resistance should be larger than 100 k . for example, users should initially select r cs to be equal to 220 k, then use equation 8 to solve for c cs . nf 1.84 k 220 m 0.89 nh 360 = = cs c because c cs is not the standard capacitance, it is implemented with two standard capacitors in parallel: 1.8 nf and 47 pf. for the best accuracy, c cs should be a 5% npo capacitor. next, solve r ph(x) by rearranging equation 7. k 93.2 k 220 m 2.1 m 0.89 = ph(x) r the standard 1% resistor for r ph(x) is 93.1 k. to prevent the saturation of the current sense amplifier when multiple phases turn on together, it is recommended to keep r ph(x) > 90 k in the 2-phase application and r ph(x) > 133 k in the 3-phase application. to avoid high frequency noise coupling across the r ph resistors, the size of the r ph resistors should not be smaller than the 0603 size. inductor dcr temperature correction with the inductor dcr used as a sense element, and copper wire being the source of the dcr, users need to compensate for temperature changes in the inductors winding. fortunately, copper has a well-known temperature coefficient (tc) of 0.39%/c. if r cs is designed to have an opposite sign but equal percentage change in resistance, then it cancels the temperature variation of the inductor dcr. due to the nonlinear nature of ntc thermistors, series resistors, r cs1 and r cs2 (see figure 12) are needed to linearize the ntc and produce the desired tc tracking. to v out sense csref cssum cscomp adp3207a 19 18 17 06582-011 place as close as possible to nearest inductor or low-side mosfet to switch nodes keep this path as short as possible and well away from switch node lines r ph3 r ph2 r ph1 r cs1 r cs2 c cs r th figure 12. temperature compensation circuit values the following procedure and equations yield values for r cs1 , r cs2 , and r th (the thermistor value at 25c) for a given r cs value: 1. select an ntc to be used based on type and value. because there is no value yet, start with a thermistor with a value close to r cs . the ntc should also have an initial tolerance of better than 5%.
adp3207a rev. 1 | page 21 of 28 | www.onsemi.com 2. based on the type of ntc, find its relative resistance value at two temperatures. temperatures that work well are 50c and 90c. these are called resistance value a (a is r th (50c)/r th (25c)) and resistance value b (b is r th (90c)/r th (25c)). note that the relative value of ntc is always 1 at 25c. 3. next, find the relative value of r cs that is required for each of these temperatures. this is based on the percentage of change needed, which is initially 0.39%/c. these are called r 1 and r 2 . () 25 1 1 1 1 ? + = t tc r (9) () 25 1 1 2 2 ? + = t tc r where: tc = 0.0039 t 1 = 50c t 2 = 90c 4. compute the relative values for r cs1 , r cs2 , and r th using () () () () () ( ) b a r a b r b a r a b r b a r r b a r cs ? ? ? ? ? ? + ? ? ? = 2 1 1 2 2 1 2 1 1 1 1 (10) () 2 1 2 1 1 1 1 cs cs cs r r a r a r ? ? ? ? = 1 2 1 1 1 1 cs cs th r r r ? ? = 5. calculate r th = r th r cs , then select the closest value of thermistor that is available. also, compute a scaling factor k based on the ratio of the actual thermistor value relative to the computed one ) ( ) ( calculated th actual th r r k = (11) 6. finally, calculate values for r cs1 and r cs2 using () () () 2 2 1 1 1 cs cs cs cs cs cs r k k r r r k r r + ? = = (12) this example starts wi th a thermistor value of 100 k and uses a vishay nths0603n04 ntc thermi stor (a 0603 size thermistor) with a = 0.3359 and b = 0.0771. from this data, r cs1 = 0.359, r cs2 = 0.729, and r th = 1.094. solving for r th yields 240 k, so 220 k is chosen, making k = 0.914. finally, r cs1 and r cs2 are 72.3 k and 166 k. choosing the closest 1% resistor values yields a choice of 71.5 k and 165 k. c out selection the required output decoupling for processors and platforms is typically recommended by intel. the following guidelines can also be used if both bulk and ceramic capacitors are in the system: ? select the total amount of ceramic capacitance. this is based on the number and type of capacitors to be used. the best location for ceramics is inside the socket; 20 pieces of size 0805 being the physical limit. additional capacitors can be placed along the outer edge of the socket. ? select the number of ceramics and find the total ceramic capacitance (c z ). combined ceramic values of 200 f to 300 f are recommended and are usually made up of multiple 10 f or 22 f capacitors. ? note that there is an upper limit imposed on the total amount of bulk capacitance (c x ) when considering the vid on-the-fly output voltage stepping (voltage step v v in time t v with error of v err ), and also a lower limit based on meeting the critical capacitance for load release at a given maximum load step i o . for a step-off load current, the current version of the imvp-6 specification allows a maximum v core overshoot (v osmax ) of 10 mv, plus 1.5% of the vid voltage. for example, if the vid is 1.150 v, then the largest overshoot allowed is 50 mv. () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + z vid o osmax o o min x c v i v r n i l c (13) z o v vid v vid v 2 o 2 max x c l nkr v v t v v r nk l c ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + 1 1 2 ) ( (14) where: ? ? ? ? ? ? ? ? ? = v err v v n k 1 (15) to meet the conditions of these equations and transient response, the esr of the bulk capacitor bank (r x ) should be less than two times the droop resistance, r o . if the c x(min) is larger than the c x(max) , the system does not meet the vid on-the-fly and/or deeper sleep exit specification and can require a smaller inductor or more phases (the switching frequency can also have to be increased to keep the output ripple the same). for example, if using 32 pieces of 10 f 0805 mlc capacitors (c z = 320 f), the fastest vid voltage change is the exit of deeper sleep, and the v core change is 220 mv in 22 s with a setting error of 10 mv.
adp3207a rev.1 | page 22 of 28 | www.onsemi.com where k = 3.1, solving for the bulk capacitance yields. () mf 0.8 f 320 v 1.150 a 34.5 mv 50 m 2.1 2 a 34.5 nh 360 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + min x c () () v 1.150 m 2.1 3.1 2 mv 220 nh 360 2 2 max x c mf 2.3 f 320 1 nh 360 mv 220 m 2.1 3.1 2 v 1.150 s 22 1 2 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + using three 330 f panasonic sp capacitors with a typical esr of 6 m each, yields c x = 0.99 mf with an r x = 2.0 m. one last check should be made to ensure that the esl of the bulk capacitors (l x ) is low enough to limit the high frequency ringing during a load change. this is tested using 2 2 o z x q r c l () nh 2 2 m 1 . 2 f 320 2 = x l (16) where: q is limited to the 2 to ensure a critically damped system. in this example, l x is about 330 ph for the three sp capacitors, which satisfies this limitation. if the l x of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased if there is excessive ringing. note that for this multimode control technique, an all-ceramic capacitor design can be used as long as the conditions of equation 13, equation 14, and equation 15 are satisfied. power mosfets for normal 20 a per phase application, the n-channel power mosfets are selected for two high-side switches and two low- side switches per phase. the main selection parameters for the power mosfets are v gs(th) , q g , c iss , c rss , and r ds(on) . because the gate drive voltage (the supply voltage to the adp3419 ) is 5 v, logic-level threshold mosfets must be used. the maximum output current i o determines the r ds(on) requirement for the low-side (synchronous) mosfets. in the adp3207a, currents are balanced between phases; the current in each low-side mosfet is the output current divided by the total number of mosfets (n sf ). with conduction losses being dominant, equation 17 shows the total power dissipated in each synchronous mosfet in terms of the ripple current per phase (i r ) and average total output current (i o ): () ) ( 2 2 12 1 1 sf ds sf r sf o sf r n i n n i d p ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? = (17) knowing the maximum output thermal current and the maximum allowed power dissipation, users can find the required r ds(on) for the mosfet. for 8-lead soic or 8-lead soic-compatible packaged mosfets, the junction to ambient (pcb) thermal impedance is 50c/w. in the worst case, the pcb temperature is 90c during heavy load operation of the notebook; a safe limit for p sf is 0.6 w at 120c junction temperature. therefore, for this example (32 a maximum thermal current), r ds(sf) (per mosfet) is less than 9.6 m for two pieces of low-side mosfet. this r ds(sf) is also at a junction temperature of about 120c; therefore, the r ds(sf) (per mosfet) should be lower than 6.8 m at room temperature, giving 9.6 m at high temperature. another important factor for the synchronous mosfet is the input capacitance and feedback capacitance. the ratio of feedback to input needs to be small (less than 10% is recommended) to prevent accidental turn-on of the synchronous mosfets when the switch node goes high. the high-side (main) mosfet has to be able to handle two main power dissipation components, conduction and switching losses. the switching loss is rela ted to the amount of time it takes for the main mosfet to turn on and off and to the current and voltage that are being switched. basing the switching speed on the rise and fall time of the gate driver impedance and mosfet input capacitance, equation 18 provides an approximate value for the switching loss per main mosfets. iss mf g mf o cc sw mf s c n n r n i v f p = 2 ) ( (18) where: n mf is the total number of main mosfets. r g is the total gate resistance (1.5 for the adp3419 and about 0.5 for two pieces of typical high speed switching mosfets, making r g = 2 ). c iss is the input capacitance of the main mosfet. the best thing to reduce switching loss is to use lower gate capacitance devices. the conduction loss of the main mosfet is given by ) ( 2 2 ) ( 12 1 mf ds mf r mf o mf c r n i n n i d p ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? = (19) where: r ds(mf) is the on-resistance of the mosfet. typically, for main mosfets, users want the highest speed (low c iss ) device, but these usually have higher on-resistance. users must select a device that meets the total power dissipation (0.6 w for a single 8-lead soic) when combining the switching and conduction losses.
adp3207a rev. 1 | page 23 of 28 | www.onsemi.com for example, using an irf7821 device as the main mosfet (four in total; that is, n mf = 4), with about c iss = 1010 pf (maximum) and r ds(mf) = 18 m (maximum at t j = 120c) and an ir7832 device as the synchronous mosfet (four in total; that is, n sf = 4), r ds(sf) = 6.7 m (maximum at t j = 120c). solving for the power dissipation per mosfet at i o = 32 a and i r = 10.7 a yields 420 mw for each synchronous mosfet and 410 mw for each main mosfet. one last consideration is the power dissipation in the driver for each phase. this is best described in terms of the qg for the mosfets and is given by () cc cc gsf sf gmf mf sw drv v i q n q n n f p ? ? ? ? ? ? + + = 2 (20) where: q gmf is the total gate charge for each main mosfet. q gsf is the total gate charge for each synchronous mosfet. this also shows the standby dissipation (i cc v cc ) of the driver. for the adp3419 , the maximum dissipation should be less than 300 mw, considering its thermal impedance is 220c/w, and the maximum temperature increase is 50c. for this example, with i cc = 2 ma, q gmf = 14 nc, and q gsf = 51 nc, there is 120 mw dissipation in each driver, which is below the 300 mw dissipation limit. see the adp3419 data sheet for more details. ramp resistor selection the ramp resistor (r r ) is used for setting the size of the internal pwm ramp. the value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. use this equation to determine a starting value r ds d r r c r a l a r = 3 (21) k 282 pf 5 m 3.4 5 3 nh 360 0.2 = = r r where: a r is the internal ramp amplifier gain. a d is the current balancing amplifier gain. r ds is the total low-side mosfet on-resistance. c r is the internal ramp capacitor value. another consideration in the selection of r r is the size of the internal ramp voltage (see equation 22). for stability and noise immunity, keep this ramp size larger than 0.5 v. in addition, larger ramp size helps to reduce output voltage ringing back during step load transient, where epwm is triggered. taking these into consideration, the value of r r is selected as 200 k. the internal ramp voltage magnitude can be calculated by sw r r vid r r f c r v d a v ? = ) 1 ( (22) v 0.77 khz 280 pf 5 k 200 v 1.150 0.061) (1 0.2 v r = ? = the size of the internal ramp can be made larger or smaller. if it is made larger, then stability and transient response improves, but thermal balance degrades. likewise, if the ramp is made smaller, then thermal balance improves at the sacrifice of transient response and stability. the factor of three in the denominator of equation 21 sets a minimum ramp size that gives an optimal balance for good stability, transient response, and thermal balance. comp pin ramp there is a ramp signal on the comp pin due to the droop voltage and output voltage ramps. this ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the pwm input () ? ? ? ? ? ? ? ? ? ? = o x sw r rt r c f n d n v v 1 2 1 (23) for this example, the overall ramp signal is found to be 2.2 v. setting the switching frequency for rpm mode operation of phase 1 during the rpm mode operatio n of phase 1, the adp3207a runs in pseudo-constant frequency, given that the load current is high enough for continuous current mode. while in discontinuous current mode, the switching frequency is reduced with the load current in a linear manner. when considering power conversion efficiency in light load, lower switching frequency is usually preferred for rpm mode. however, the v core ripple specification in the imvp-6 sets the limitation for lowest switching frequency. therefore, depending on the inductor and output capacitors, the switching frequency in rpm mode can be equal, larger, or smaller than its counterpart in pwm mode. a resistor between pin vrpm and pin rrpm sets the pseudo constant frequency as k 0.5 f c r v d) (1 a v 1.0 v r 2 sw r r vid r vid t ? ? + = rpm r (24) where: a r is the internal ramp amplifier gain. c r is the internal ramp capacitor value. r r is an external resistor on the rampadj pin to set the internal ramp magnitude.
adp3207a rev.1 | page 24 of 28 | www.onsemi.com because r r = 280 k, the following resistance sets up 300 khz switching frequency in rpm operation. k 6 . 80 500 khz 300 pf 7 k 280 150 . 1 ) 061 . 0 1 ( 2 . 0 v 0 . 1 v 150 . 1 k 237 2 = ? ? + = rpm r current-limit setpoint to select the current-limit setpoint, the resistor value for r lim needs to be found. the current-limit threshold for the adp3207a is set with a 1.7 v source (v lim ) across r lim with a gain of 13 mv/a. r lim can be found by o lim lim lim lim r i v a r = (25) for values of r lim greater than 500 k, the current limit may be lower than expected, so some adjustment of r lim may be needed. here, i lim is the average current limit for the output of the supply. in this example, if choosing 55 a for i lim , r lim is 190 k, which is close to a standard 1% resistance of 191 k. the per-phase current limit described earlier has its limit determined by 2 ) ( ) ( r max ds d bias r max comp phlim i r a v v v i + ? ? ? (26) for the adp3207a, the maximum comp voltage (v comp(max) ) is 3.2 v, the comp pin bias voltage (v bias ) is 1.0 v, and the current balancing amplifier gain (a d ) is 5. using a v r of 0.77 v, and a r ds(max) of 3.8 m (low-side on-resistance at 150c) results in a per-phase limit of 79 a. although this number seems high, this current level can only be reached with an absolute short at the output and the current-limit, latch-off function shutting down the regulator before overheating occurs. this limit can be adjusted by changing the ramp voltage v r . however, users should not set the per-phase limit lower than the average per-phase current (i lim /n). there is also a per-phase initial duty-cycle limit at maximum input voltage r bias max comp min lim v v v d d ? = ) ( (27) for this example, the duty-cycle limit at maximum input voltage is 0.18 when d is 0.061. feedback loop compensation design optimized compensation of the adp3207a allows the best possible response of the regulator s output to a load change. the basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistance (r o ). with the resistive output impedance, the output voltage droops in proportion with the load current at any load current slew rate. this ensures the optimal positioning and minimizes the output decoupling. with the multimode feedback structure of the adp3207a, users need to set the feedback compensation to make the converter output impedance work in parallel with the output decoupling. several poles and zeros are created by the output inductor and decoupling capacitors (output filter) that need to be compensated for. a type-three compensator on the voltage feedback is adequate for proper compensation of the output filter. equation 28 to equation 36 is intended to yield an optimal starting point for the design; some adjustments can be necessary to account for pcb and component parasitic effects (see the tuning procedure for adp3207a section). the first step is to compute the time constants for all of the poles and zeros in the system () vid o x rt id rt l ds d o e v r c n v d n l v v r r a r n r ? + + + = 1 2 (28) () x o o x o x a r r r r l r r c t ' ' ? + ? = (29) ( ) x o x b c r r r t ? + = ' (30) e vid sw ds d rt c r v f r a l v t ? ? ? ? ? ? ? ? ? = 2 (31) () o z o x o z x d r c r r c r c c t + ? = ' 2 (32) where: r is the pcb resistance from the bulk capacitors to the ceramics. r ds is the total low-side mosfet on-resistance per phase. for this example, a d is 5, v rt = 1. 5 v, r is approximately 0.4 m (assuming an 8-layer motherboard), and l x is 250 ph for the four panasonic sp capacitors. the compensation values can be solved using the following: b e a o r r t r n c = a (33) a c a c t r = (34) b b b r t c = (35) a d fb r t c = (36) the standard values for these components are subject to the tuning procedure, as introduced in the c in selection and input current d i /d t reduction section.
adp3207a rev. 1 | page 25 of 28 | www.onsemi.com c in selection and input current d i /d t reduction in continuous inductor-current mode, the source current of the high-side mosfet is approximately a square wave with a duty ratio equal to n v out /v in and an amplitude of 1-nth the maximum output current. to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current happens at the lowest input voltage, and is given by 1 1 ? = d n i d i o crms (37) a 3 . 10 1 64 0.1 2 1 a 44 164 . 0 = ? = crms i in a typical notebook system, the battery rail decouplings are mlcc capacitors or a mixture of mlcc capacitors and bulk capacitors. in this example, the input capacitor bank is formed by eight pieces of 10 f, and 25 v mlcc capacitors with a ripple current rating of about 1.5 a each. soft transient setting as described in the soft transient section, during the soft transient, the slew rate of v core reference voltage change is controlled by the stset pin capacitance. because the timing of deeper sleep exit is critical, the stset pin capacitance is set to satisfy the fast deeper sleep exit slew rate as e c stset slewrate c 4 2 a 8 = (38) where: 8 a is the source/sink current of the stset pin. slewrate c4e is the voltage slew rate during deeper sleep exit, defined as 10 mv/s in the imvp-6 specification. c stset equals 400 pf, with the closest standard capacitance at 390 pf. selecting thermal monitor components for single-point hot spot thermal monitoring, simply set r ttset1 equal to the ntc thermistors resistance at the alarm temperature (see figure 13). for example, if the vrtt alarm temperature is 100c using a vishey thermistor (nths- 0603n011003j) with a resistance of 100 k at 25c, and 6.8 k at 100c, simply set r ttset1 = r th1 (100c) to 6.8 k. adp3207a vcc ttsense vrtt r r 5v 06582-012 31 30 r th1 c tt r ttset1 figure 13. single-point thermal monitoring multiple-point hot spot thermal monitoring can be implemented as shown in figure 14. if any of the monitored hot spots reach alarm temperature, the vrtt signal is asserted. the following calculation sets the alarm temperature: rature alarmtempe th ref fd ref fd ttset r v v v v r 1 1 ? ? ? + = (39) where v fd is the forward drop voltage of the parallel diode. because the forward current is very small, the forward drop voltage is very low (100 mv). assuming the same 100c alarm temperature used in the single-spot thermal monitoring example, and the same vishay thermistor , then equation 39 leads to r ttset = 7.37 k, whose closest standard resistor is 7.32 k (1%). ? 06582-013 a dp3207a vcc ttsense vrtt r r 5v 31 30 r ttsetn r thn r th2 r th1 r ttset2 r ttset1 v fd figure 14. multiple-point thermal monitoring the number of hot spots monitored is not limited. the alarm temperature of each hot spot can be set differently by playing different r ttset1 , r ttset2 , and r ttsetn . tuning procedure for adp3207a 1. build the circuit based on compensation values computed from equation 1 to equation 39. 2. hook-up the dc load to the circuit. turn the circuit on and verify operation. check for jitter at no load and full load. dc loadline setting 3. measure the output voltage at no load (v nl ). verify that it is within tolerance. 4. measure the output voltage at full load and at cold (v flcold ). let the board set for ~10 minutes at full load and measure the output (v flhot ). if there is a change of more than a few mv, then adjust r cs1 and r cs2 using equation 40 and equation 41. flhot nl flcold nl old cs new cs v v v v r r ? ? = ) ( 2 ) ( 2 (40) 5. repeat step 4 until cold and hot voltage measurements remain the same. 6. measure output voltage from no load to full load using 5 a steps. compute the load line slope for each change and then average it to get the overall load line slope (r omeas ).
adp3207a rev.1 | page 26 of 28 | www.onsemi.com 7. if r omeas is off from r o by more than 0.05 m, use the following to adjust the r ph values o omeas old ph new ph r r r r = ) ( ) ( (41) 8. repeat step 6 and step 7 to check load line and repeat adjustments if necessary. 9. once completed with dc load line adjustment, do not change r ph , r cs1 , r cs2 , or r th for the rest of procedure. 10. measure output ripple at no load and full load with a scope to make sure it is within specification. ac loadline setting 06582-014 v acdrp v dcdrp figure 15. ac loadline waveform 11. remove the dc load from the circuit and hook up the dynamic load. 12. hook up the scope to the output voltage and set it to dc coupling with the time scale at 100 s/div. 13. set the dynamic load for a transient step of about 40 a at 1 khz with a 50% duty cycle. 14. measure the output waveform (using the dc offset on scope to see the waveform, if necessary). try to use the vertical scale of 100 mv/div or finer. 15. users should see a waveform that is similar to the one in figure 16. use the horizontal cursors to measure v acdrp and v dcdrp as shown. do not measure the undershoot or overshoot that occurs immediately after the step. 16. if the v acdrp and v dcdrp are different by more than a couple of mv, use the following to adjust c cs . (note that users may need to parallel different values to get the right one due to the limited standard capacitor values available. it is also wise to have locations for two capacitors in the layout for this.) dcdrp acdrp old cs new cs v v c c = ) ( ) ( (42) 17. repeat step 15 and step 16. repeat adjustments if necessary. once completed, do not change c cs for the rest of the procedure. 18. set dynamic load step to maximum step size. do not use a step size larger than needed. verify that the output waveform is square, which means v acdrp and v dcdrp are equal. note: make sure that the load step slew rate and turn-on are set for a slew rate of ~150 a/s to 250 a/s (for example, a load step of 50 a should take 200 ns to 300 ns) with no overshoot. some dynamic loads have an excessive turn-on overshoot if a minimum current is not set properly (this is an issue if using a vtt tool). initial transient setting 19. with dynamic load still set at the maximum step size, expand the scope time scale to see 2 s/div to 5 s/div. a waveform that has two overshoots and one minor undershoot can result (see figure 16). here, v droop is the final desired value. 06582-015 v droop v tran1 v tran2 figure 16. transient setting waveform, load step 20. if both overshoots are larger than desired, make the following adjustments in the order they appear. note that if these adjustments do not change the response, users are limited by the output decoupling. in addition, check the output response each time a change is made, as well as the switching nodes to make sure they are still stable. a. make ramp resistor larger by 25% (r ramp ). b. for v tran1 , increase c b or increase switching frequency. c. for v tran2 , increase r a and decrease c a , both by 25%. 21. for load release (see figure 17), if v tranrel is larger than the imvp-6 specification, there is not enough output capacitance. either more capacitance is needed or the inductor values need to be smaller. if the inductors are changed, then start the design over using equation 1 to equation 39 and this tuning guide. 06582-016 v droop v tranre l figure 17. transient setting waveform, load release
adp3207a rev. 1 | page 27 of 28 | www.onsemi.com layout and component placement the following guidelines are recommended for optimal performance of a switching regulator in a pc system. general recommendations for effective results, at least a 4-layer pcb is recommended. this allows the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the rest of the power delivery current paths. note that each square unit of 1 ounce copper trace has a resistance of ~0.53 m at room temperature. when high currents need to be routed between pcb layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths are minimized, and the via current rating is not exceeded. if critical signal lines (including the output voltage sense lines of the adp3207a) must cross through power circuitry, a signal ground plane should be interposed between those signal lines and the traces of the power circuitry. this serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. an analog ground plane should be used around and under the adp3207a for referencing the components associated with the controller. tie this plane to the nearest output decoupling capacitor ground. it should not be tied to any other power circuitry to prevent power currents from flowing in it. the best location for the adp3207a is close to the cpu corner where all the related signal pins are located: vid0 to vid6, psi , v cc sense, and v ss sense. the components around the adp3207a should be located close to the controller with short traces. the most important traces to keep short and away from other traces are the fb and cssum pins (refer to figure 11 for more details on layout for the cssum node.) the mlcc for the vcc decoupling should be placed as close to the vcc pin as possible. in addition, the noise filtering capacitor on the ttsense pin should also be as close to that pin as possible. the output capacitors should be connected as closely as possible to the load (or connector) that receives the power (for example, a microprocessor core). if the load is distributed, then the capacitors should also be distributed, and generally in proportion to where the load tends to be more dynamic. power circuitry avoid crossing any signal lines over the switching power path loop. this path should be routed on the pcb to encompass the shortest possible length to minimize radiated switching noise energy (that is, emi) and conduction losses in the board. failure to take proper precautions often results in emi problems for the entire pc system as well as noise-related operational problems in the power converter control circuitry. the switching power path is the loop formed by the current path through the input capacitors and the power mosfets, including all interconnecting pcb traces and planes. the use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand wi th minimal voltage loss. whenever a power-dissipating component (for example, a power mosfet) is soldered to a pcb, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. two important reasons for this are: improved current rating through the vias, and improved thermal performance from vias extended to the opposite side of the pcb where a plane can more readily transfer the heat to the air. make a mirror image of any pad being used to heat sink the mosfets on the opposite side of the pcb to achieve the best thermal dissipation to the air around the board. to further improve thermal performance, the largest possible pad area should be used. the output power path should also be routed to encompass a short distance. the output power path is formed by the current path through the inductor, the output capacitors, and the load. for best emi containment, use a solid power ground plane as one of the inner layers extending fully under all the power components. it is important for conversion efficiency that mosfet drivers, such as adp3419 , are placed as close to the mosfets as possible. thick and short traces are required between the driver and mosfet gate, especially for the sr mosfets. ground the mosfet drivers gnd pin through the closest vias. signal circuitry the output voltage is sensed and regulated between the fb pin and the fbrtn pin, which connects to the signal ground at the load. to avoid differential mode noise pickup in the sensed signal, the loop area should be small. therefore, route the fb and fbrtn traces adjacent to each other atop the power ground plane back to the controller. to filter any noise from the fbrtn trace, using a 1000 pf mlcc is suggested. it should be placed between the fbrtn pin and local ground and as close to the fbrtn pin as possible. connect the feedback traces from the switch nodes as close as possible to the inductor. the cs ref signal should be kelvin connected to the center point of the copper bar, which is the v core common node for the inductors of all phases. on the back side of the adp3207a package, a metal pad can be used as the device heat sink. in addition, running vias under the adp3207a is not recommended because the metal pad can cause shorting between vias.
adp3207a rev.1 | page 28 of 28 | www.onsemi.com outline dimensions compliant to jedec standards mo-220-vjjd-2 1 40 10 31 30 21 20 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indicator 5.75 bcs sq 12 max 0.30 0.23 0.18 0.20 ref seating plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarity 0.08 0.80 max 0.65 typ 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bot tom view) exposed paddle can be grounded. 101306-a figure 18. 40-lead lead frame chip scale package [lfcsp_vq] 6 mm 6 mm body, very thin quad (cp-40-1) dimensions shown in millimeters ordering guide model temperature range package description package option ordering quantity ADP3207AJCPZ-RL 1 0c to 100c 40-lead lead frame chip scale package [lfcsp_vq] cp-40-1 2,500 1 z = pb-free part. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes witho ut further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without li mitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specif ications can and do vary in different applications and actu al performance may vary over time. all operating parameters, including ?typicals? must be validated for each custom er application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surg ical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized app lication, buyer shall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone: 303-675-2175 or 800-344-3860 toll free usa/canada fax: 303-675-2176 or 800-344-3867 toll free usa/canada email: orderlit@onsemi.com n. american technical support: 800-282-9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81-3-5773-3850 on semiconductor website: www.onsemi.com order literature: http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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